Memory Subsystem Post-Silicon Engineer (UMC Lab Liaison)

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THE ROLE:

The Memory Subsystem team is seeking aUMC Lab Liaison Engineerto drive post-silicon bring-up, debug, and feature enablement for DDR memory subsystems across AMD's next-generation client and server platforms.

This roleoperatesat the intersection ofsilicon validation, firmware, design, and SoC integration, serving as thetechnical point-of-contact for UMC-related issues during bring-up and production ramp. The engineer will own end-to-end execution of memory subsystem validation - frominitialsilicon bring-up through feature enablement, performance tuning, and customer issue resolution.

You will work on LPDDR5/LPDDR5X/DDR5 technologies, enabling high-performance memory systems and ensuring first-pass silicon success across multiple programs.

THE PERSON:

You are a hands-on debug engineer who thrives in exciting, challenging bringup environments and consistently takes endtoend ownership of problems-from identifying the root cause to driving cross-team resolution. You are equally comfortable debugging waveform-level issues, collaborating closely with firmware and BIOS teams, aligning multiple engineering organizations, and communicating clearly with leadership during critical program phases. You bring a strong sense of ownership, urgency, and accountability, and you are motivated by solving complex system-level problems that directly influence overall product success.

KEY RESPONSIBILITIES:

• Own UMCrelated postsilicon bringup, debug, and feature enablement across client and server programs
• Serve as the primary liaison between Validation, Firmware, Design, and SoC teams, acting as a technical bridge across functions
• Drive endtoend issue ownership by identifying, analyzing, and pushing systemlevel memory issues to full resolution
• Debug memory subsystem interactions spanning controller, PHY, firmware, and platform components
• Perform deep rootcause analysis using waveforms, lab instrumentation data, logs, and crossenvironment correlation
• Translate lowlevel technical findings into systemlevel impact, risks, and clear action plans for stakeholders
• Develop and execute validation plans for memory subsystem features, including functional, performance, latency, bandwidth, and powerstate behavior
• Track issues through closure using JIRA/debug flows and ensure alignment across teams in fastpaced bringup environments with shifting priorities
• Provide concise, ongoing status updates, risk assessments, and debug summaries to program leadership
• Support customerfacing issues and escalations with timely technical investigation and resolution
• Contribute to improvements in postsilicon debug methodology, infrastructure, workflows, and crossteam communication

PREFERRED EXPERIENCE:

• Strong understanding of DDR memory systems (DDR5 / LPDDR5) and controller/PHY interactions
• Handson experience with postsilicon bringup and validation in a lab environment
• Familiarity with BIOS, firmware flows, and lowlevel hardware initialization sequences
• Experience debugging power states, clocking, resets, and sequencing behavior
• Knowledge of ECC, RAS, memory reliability features, and systemlevel performance characteristics
• Background working with SoClevel validation, integration teams, and multiIP subsystem interactions
• Proficiency with logic analyzers, oscilloscopes, and silicon debug tools
• Experience using Python or similar scripting languages for automation, log parsing, or data analysis
• Demonstrated ability to operate effectively in fastmoving bringup environments and communicate across engineering disciplines without direct authority
• Experience driving collaborative issue resolution between Design, Firmware, and Validation teams while maintaining clear ownership

ACADEMIC CREDENTIALS:

* Bachelor's degree in electrical or computer engineering and relevant experience, or
*Master'sor PhD degree in Electrical or Computer Engineering with relevant experience

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.